Timing Constraints - Revisited 
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 Timing Constraints - Revisited

You might switch your code over to a state machine (case structure
inside a while loop) approach if the combination of sequences and
while loops is getting too messy.  In the state machine you should be
able to easily monitor time passed.  Set a constant loop rate using
the "Wait until next ms multiple" and then just count how many
iterations have taken place.

To help monitor your current code's timing, you can use the tick count
vi.  Subtract one tick count's value from another to get the time

Sun, 15 Aug 2004 06:34:38 GMT  
 [ 1 post ] 

 Relevant Pages 

1. ALLKEY.PRG revisited one more time!

2. Instruction timings, revisited

3. It is time to revisit Logo!

4. Timing Constraints

5. Timing constraints in Verilog source code

6. Automatic creation of timing constraints for multiple clock designs

7. Timing constraints

8. Negative Timing Constraints

9. VHDL XILINX Timing Constraints

10. Constraint Logic Programming over time

11. Constraint Programming for time critical applications

12. null ranges and index constraints (was constraint error question)


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