Free "simple" 16 bits Forth soft core for FPGA or ASIC ? 
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 Free "simple" 16 bits Forth soft core for FPGA or ASIC ?

As an engineer interested in wireless embedded solution, I had raised some
questions related to commercial offer of Forth chip/stack machine as a soft
VDHL core for FPGA or ASIC target a couple of weeks ago here in c.l.f. From
the answers  I got + readings , I have retained the following conclusions:

As far as targeting a Forth CPU as a (small) part of an large modern ASIC
besides other macroblocks, I don't have seen any example, I wonder if it
ever happens ,
As far as targetting Forth into FPGA (possibly besides other specific
harware), it is also quite a unfrequent path today:

- the FPGA usage in embedded solution is far from replacing the usage of
usual microcontrollers (8051, 6809, ..) because of:
     - cost: only the simplest FPGAs is a few $ today (of course it is
decreasing..)
     - power consumption: FPGAs are not necessary very good at that.
     - existence of huge legacy codes
     - FPGAs are not a miniature world as opposed to some microcontrollers
with their ADCs, DACs, driver, etc..,so a FPGA may not come alone in the
system design (note that it may change too)
     - sometimes you simply don't need to put extra specific hardware and
are not necessary seeking for better processing power: only development time
matters and Forth satisfies you just for that.
     - probably also simply habits

- There are a lot of individual FPGA attempts and projects in differents
places to be seen on the web, but rather from people wanting to design on
their own for fun or educational purpose, or not worried by designing
something specifics, including also the assembler, that is to say: something
that an engineer with limited Forth CPU knowledge can not afford in a
general purpose company within constraints like schedule,...

- Hovewer, a soft VHDL (or verilog) implementation of a CPU (getting closer
to the virtual Forth model) would be quickly benefitial in terms of
performance and size implementation: one would be far away from today's
performances of some microcontrollers (I have seen the benchmarks on
Forth.Inc web site from which I understand that the ratio (Forth instruction
cycle / machine cycle) is frankly poor for old micros).

What would be nice in an ideal world (for me) is to have (hopefully many)
Forth companies proposing commercial Forth system offers for a single
relatively simple, cheap and well known Forth CPU soft core. A company PTSC
provides the Ignite1 processor as a soft core, but this is a race horse
which may be oversized (in size and price I think) in many situations to my
opinion.

More ideally, the license of the soft core should be free (that is the
reference model in VHDL, not necessary the synthetized and routed core). The
prime reason to wish it free is for me not so much a question of cost (up to
a certain level) but rather to be more or less independent from the core
provider. From a general point of view, being inside a quite big company,
focusing on my application field, I am not in favor of using free Forth
system but rather of purchasing commercial Forth system, for their support
namely. Getting dependent of a Forth system provider is one normal thing,
getting in addition dependent of a Forth CPU soft core provider is another
thing that makes the deal too uncertain and complicate for many cases.

A good example of such an ideal soft core is RTX2000 (as far as I feel):
- it should not be very big (although I wonder how many kgates it has)
- it is 16 bits already / only
- it has quite advanced features for arithmetic and stack controls and
multitasks
- the internal dual stacks are easily integrable into (of course an ASIC or)
FPGAs which generally have internal RAM zone which can be partitionned at
willing,
- etc..

Yes, all that is easy speech from me, as I don't exactly realize what means
"free Forth CPU" in practice. Also, "simple" may have a different meaning to
people. Still, a few questions:

Q1: does anybody have heard of any such "simple" Forth soft free core
initiative, for example under gpl (I went to F-CPU web site but they are
targeting an ambitious CPU far away from that pragmatic needs)?
Q2: is there any chance to see some former CPU forth designs to fall in the
public domain ?
Q3: How are these former designs like RTX2000 considered today by the team
who designed them  10-20 years ago ? Said another way, would it be drastic
changes if new design of same size and complexity would have to be done
today?

I think that the lack of a simple but modern reference Forth CPU plateform
could block the entering of new incomers into embedded system Forth user
communitity, while FPGA usage is widespreading, at least as far as non Forth
specialist engineers are concerned. By non Forth specialist, I mean people
who can still spend on average 80% of their time on coding their
application, and not on fully understanding software tools, CPU, and so on .

-------------------------------------------------------------------------
Renaud Dor

Thomson multimedia - Corporate Research Rennes
Tel :  (33) 2 99 27 33 13    Fax : (33) 2 99 27 30 58

THOMSON multimedia R&D France
1, avenue de Belle Fontaine

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Mon, 15 Mar 2004 17:43:12 GMT  
 Free "simple" 16 bits Forth soft core for FPGA or ASIC ?

Quote:

> I think that the lack of a simple but modern reference Forth CPU plateform
> could block the entering of new incomers into embedded system Forth user
> communitity, while FPGA usage is widespreading, at least as far as non Forth
> specialist engineers are concerned. By non Forth specialist, I mean people
> who can still spend on average 80% of their time on coding their
> application, and not on fully understanding software tools, CPU, and so on .

I suppose you've already visited www.ultratechnology.com/chips.htm

The problem, I think, is to find a CPU design that works reasonably
well in many processes. Something optimized for Xilinx might not be
efficient on Altera and vice versa. I assume that an ASIC flow would
accommodate a design optimized for an FPGA, so IMHO a soft Forth chip
should be designed with FPGA implementation in mind.

Most FPGAs have block RAM available, which I'd use for stacks. Having
256 cells available in each stack would be good for multitasking. I'd
define a minimal number of registers to make the thing work and that
would be the baseline CPU. It would implement 20 or 30 instructions
out of a possible 64 or 128. A Forth system could use this baseline
architecture. If you need more performance, you define new
instructions.

A couple of years ago I wrote a model whose block diagram is at
http://www.tinyboot.com/e16.pdf . I would remove the pipelining in the
decoder and make a better control unit, but it's a useful approach.

8-bit instructions are a good fit for FPGAs. Without floor planning,
you get around 25 MIPs peak, which requires a new instruction every
40ns. A byte-wide external RAM or fast EPROM should be able to supply
this. Most data access would be on-chip, so going to external RAM for
16-bit data (over an 8-bit data bus) might not be a big performance
hit.

Many college VHDL synthesis courses include a simple CPU design as one
of the projects, so designing a simple Forth CPU can't be that tough.
In the class I took, it took me 20 or 30 hours to get a model working
and massage it to get a clean synthesis. The CPU was a 16-bit
register-based machine that ran at 28 MHz on a Xilinx 4000 type part.

If somebody writes a soft Forth chip that fits well in Xilinx, I'll
write a Forth for it. I would have written one for the MSL16, but that
chip was just too minimal.

--
Brad Eckert

"I love the smell of solder flux in the morning"



Tue, 16 Mar 2004 04:14:06 GMT  
 Free "simple" 16 bits Forth soft core for FPGA or ASIC ?
Quote:

> I think that the lack of a simple but modern reference Forth CPU plateform
> could block the entering of new incomers into embedded system Forth user
> communitity, while FPGA usage is widespreading, at least as far as non Forth
> specialist engineers are concerned. By non Forth specialist, I mean people
> who can still spend on average 80% of their time on coding their
> application, and not on fully understanding software tools, CPU, and so on .

I think the key here is the testbench. Soft Forth CPU implementations
should be able to vary widely. The testbench will be the real
reference, acting as the real functional description. If your CPU
design passes the testbench (and small CPUs aren't that hard to
design) then your Forth code should be fine.

I would suggest a 16-bit CPU with 8-bit instructions. The testbench
would test 20 or 30 mandatory instructions. There are some free VHDL
simulators that will be able to run a testbench and a Forth CPU model.

I'm working on a paper describing the design process used to come up
with a soft Forth chip and its instruction set. I'll post a link when
it's done.

--
Brad Eckert



Wed, 17 Mar 2004 09:42:36 GMT  
 
 [ 3 post ] 

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