Definitive S/370 Feature List (Re: ICM & STCM) 
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 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:

> 6 pages --
>   2 for the instruction
>   2 for the data area
>   2 for the translate table

Except that the translate table is part of the data. BTW, is there any case where
a noninterruptible instruction can exceed 2 instruction pages and 4 data pages?
Quote:

> -- Steve Myers



Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:

>OK, again.  This is the maximum pages required.  The question is, which
>pages are required?  If the second argument (translation table) crosses
>a page boundary, it is possible that one page or the other is not
>required.  The machine will not page fault for that page.  It is required
>not to.  The requirement exists because the page might not exist.

It is difficult to guess how the hardware implements this.  It almost
seems as if the processor might have to fetch both data and table
into buffers, do the translation in the buffers, then write back the
results.  Principles of Operation talks about a trial execution to
determine how much of the table is required.  But if other cpus or
channels could be modifying the data, then no trial execution can be
decisive unless the data is prefetched and the later full execution
uses the prefetched data.  Since the instruction is supposed to act
as if data is processed one byte at a time (in case data and table
overlap), the table would also need to be partially prefetched or the
processing would have to ensure that the overlapped part of the table
came from the prefetched data.


Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:


>>OK, again.  This is the maximum pages required.  The question is, which
>>pages are required?  If the second argument (translation table) crosses
>>a page boundary, it is possible that one page or the other is not
>>required.  The machine will not page fault for that page.  It is required
>>not to.  The requirement exists because the page might not exist.
>It is difficult to guess how the hardware implements this.  It almost
>seems as if the processor might have to fetch both data and table
>into buffers, do the translation in the buffers, then write back the
>results.  Principles of Operation talks about a trial execution to
>determine how much of the table is required.  But if other cpus or
>channels could be modifying the data, then no trial execution can be
>decisive unless the data is prefetched and the later full execution
>uses the prefetched data.  Since the instruction is supposed to act
>as if data is processed one byte at a time (in case data and table
>overlap), the table would also need to be partially prefetched or the
>processing would have to ensure that the overlapped part of the table
>came from the prefetched data.

Well, other CPUs modifying the data could be a problem.  Probably it is
undefined in that case.  The trial execution, load only, takes care of getting
all needed pages in memory before any results are stored.  You are right,
though, if operand one was changed between the trial and the real execution,
it could access non-existent pages.  In this case, my best guess is that
it page faults anyway.  Or maybe worse.  It could give access exception in
that case.   According to POp, it is a multiple-access instruction, and
references section 5.13.9.2.  It doesn't say what happens if you modify
operand one while it is running, though.

They do have as a example, that MP (multiply decimal) might do repeated
add, and if the operand is changed while running, it might add some of
one value and some of another value.  

-- glen



Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:


>Well, other CPUs modifying the data could be a problem.  Probably it is
>undefined in that case.

Right.  This is described as being unpredictable.

Quote:
>                         The trial execution, load only, takes care of getting
>all needed pages in memory before any results are stored.  You are right,
>though, if operand one was changed between the trial and the real execution,
>it could access non-existent pages.  In this case, my best guess is that
>it page faults anyway.

Right.  That is the problem.  A page fault is supposed to result in the
operation being nullified, so should not occur if values have already
been stored.

However, looking at the fine print, this does seem to be covered in
chapter 5.  There is a section "Exceptions to Nullification and
Suppression".  The following page mentions the trial execution, and
implies that if another CPU modifies after the trial execution, then
the final execution may page fault and yet the result field may have
been changed.



Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:



> >> One important case is TR, where the possible memory reference addresses
> >> cannot be known in advance.

> >No way. The possible addresses are in the range destination to destination + length
> >(really length-1) and table to table plus 255. That covers a maximum of four pages.

> It is not necessarily table to table+255, if the data to be translated does
> not have that range.  If table is close to a page boundary, it is possible
> that there is no reference to the page that table or table+255 are on.
> It is not required that both pages exist if there is no reference to them.

> At least as of S/370, TR won't page fault if the table entries needed by
> the data to be translated exist.  They may have changed this by S/390, but
> I would be surprised.

> -- glen

Actually, it is required that ED/EDMK/TR/TRT not cause

an actual page fault if they do not *use* data out of

the page.  This leads to the `pretest execution' if

the data *could* cross (note ED/EDMK also have no

second length, it is determined by the mask AND the

data from the source).  One of my *favorite* additions

to the POO for 370 DAT included the case where another

CPU or channel modifies the data _between_ the pretest

and the actual instruction execution (ie. makes the

Translate use data across a page boundry by changing

the source data).  The POO specifies that the results

are undetermined _and_ that a page fault may or may not

occur.

   - Brent



Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:

> > 6 pages --
> >   2 for the instruction
> >   2 for the data area
> >   2 for the translate table

> Except that the translate table is part of the data. BTW, is there any case where
> a noninterruptible instruction can exceed 2 instruction pages and 4 data pages?

> > -- Steve Myers

Sure, the Execute instruction can cause 2 more instruction

pages.  That would give 4 instruction and 4 data pages.

In addition, you can need more pages when running some of

the more obscure operating system assist ops.

   - Brent



Mon, 29 Jan 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:

> I think you can still get an S0C6 if you mis-align a CVB, CVD, CS, or CDS.
> Or if your target for an EX is not half-word aligned. Or if you branch to a
> odd address. But not for "normal" instructions. I remember going into an
> application where throughout it had code sequences such as:

>    MVC HALFWORD,0(R3)
>    LH    R2,HALFWORD

> and
>    STH R2,HALFWORD
>    MVC 0(2,R3),HALFWORD

> And this was *not* '60s code! It had been written around 1989!

But obviously by a 60's programmer. I wonder where s/he was during
the seventies and eighties? Perhaps in prison for crimes against
humanity; or maybe on a commune in New Mexico???

--
Bill



Mon, 05 Feb 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:

> > I think you can still get an S0C6 if you mis-align a CVB, CVD, CS, or CDS.
> > Or if your target for an EX is not half-word aligned. Or if you branch to a
> > odd address. But not for "normal" instructions. I remember going into an
> > application where throughout it had code sequences such as:

> >    MVC HALFWORD,0(R3)
> >    LH    R2,HALFWORD

> > and
> >    STH R2,HALFWORD
> >    MVC 0(2,R3),HALFWORD

> > And this was *not* '60s code! It had been written around 1989!

> But obviously by a 60's programmer. I wonder where s/he was during
> the seventies and eighties? Perhaps in prison for crimes against
> humanity; or maybe on a commune in New Mexico???

This is scardcely an appropriate response.  The code may have
been required to run on a S/360 or lookalike.

- Show quoted text -

Quote:

> --
> Bill



Tue, 06 Feb 2001 03:00:00 GMT  
 Definitive S/370 Feature List (Re: ICM & STCM)

Quote:


> > > I think you can still get an S0C6 if you mis-align a CVB, CVD, CS, or CDS.
> > > Or if your target for an EX is not half-word aligned. Or if you branch to a
> > > odd address. But not for "normal" instructions. I remember going into an
> > > application where throughout it had code sequences such as:

> > >    MVC HALFWORD,0(R3)
> > >    LH    R2,HALFWORD

> > > and
> > >    STH R2,HALFWORD
> > >    MVC 0(2,R3),HALFWORD

> > > And this was *not* '60s code! It had been written around 1989!

> > But obviously by a 60's programmer. I wonder where s/he was during
> > the seventies and eighties? Perhaps in prison for crimes against
> > humanity; or maybe on a commune in New Mexico???

> This is scardcely an appropriate response.  The code may have
> been required to run on a S/360 or lookalike.

Please name one processor in nine{*filter*}-eighty-nine, when the code was
written that would have had this problem ? ? ? Oh, and the federal gov't
doesn't count.

And Robin, lighten up... Don't take it so personally... It's not an
attack on you, unless you were the one that wrote the offending code!

--
Bill



Tue, 06 Feb 2001 03:00:00 GMT  
 
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