ICM & STCM 
Author Message
 ICM & STCM

Not yet mentioned...  Data boundry alignment stopped being
required with S/370.  Only privileged instructions could get an
0C_    AHHHHGG!!!! Been so long since I got one, I forget what the
program interrupt code is for boundry alignment...  ;-)

Also, if you hit the PoPs there is a feature comparision list:
http://www.*-*-*.com/ :80/cgi-bin/bookmgr/bookmgr.cmd/BOOKS/DZ9A...



Tue, 23 Jan 2001 03:00:00 GMT  
 ICM & STCM

Quote:

>Not yet mentioned...  Data boundry alignment stopped being
>required with S/370.  Only privileged instructions could get an
>0C_    AHHHHGG!!!! Been so long since I got one, I forget what the
>program interrupt code is for boundry alignment...  ;-)

It was 0C6, "specification exception," and good riddance to it!

Of course, many microprocessors still in use have memory
alignment requirements, and very annoying it is, too.

As I recall, this was one of the errors that could cause an imprecise
interrupt (0C0) on the (System/360) model 91.



Tue, 23 Jan 2001 03:00:00 GMT  
 ICM & STCM

Quote:

> I believe the 370 came standard with packed decimal and floating point
> hardware.

Floating point was still sold as an option.  The saleman for the first
145 sold in the Chicago area blew it and didn't order the floating point
feature.  MVT couldn't get through NIP.  An emergency EC had to be
ordered - it was nothing by a floppy with a different microcode load.

The same customer, who had 360/67 experience, noticed that the emulator
used a LRA instruction so the unannounced virtual addressing was out of
the bag.  Of course the control panel that displayed both real and
logical addresses was another hint.

Bob Eltgroth



Tue, 23 Jan 2001 03:00:00 GMT  
 ICM & STCM


: >
: > : 390 added the access register stuff (LAE STAM, LAM, etc.) The
: > : immediate and relative branch stuff is very recent and only works on
: > : CMOS machines.
: >
: > Access Registers were available in ESA/370 architecture; before ESA/390.
: > --
: > | Edward E. Jaffe                | Voice:      (310) 338-0400 x318     |
: > | Mgr., Research & Development   | Facsimile:  (310) 338-0801          |

: > | 9841 Airport Blvd, Suite 700   | IBM Mail:   USS24J24 at IBMMAIL     |
: > | Los Angeles, CA 90045          | Web page:   www.phoenixsoftware.com |
: >

: Yes, you're right, they were! So what "significant" features were
: added by IBM to change S370 to S390?

Sysplex.
--
| Edward E. Jaffe                | Voice:      (310) 338-0400 x318     |
| Mgr., Research & Development   | Facsimile:  (310) 338-0801          |

| 9841 Airport Blvd, Suite 700   | IBM Mail:   USS24J24 at IBMMAIL     |        
| Los Angeles, CA 90045          | Web page:   www.phoenixsoftware.com |



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution
I think you can still get an S0C6 if you mis-align a CVB, CVD, CS, or CDS.
Or if your target for an EX is not half-word aligned. Or if you branch to a
odd address. But not for "normal" instructions. I remember going into an
application where throughout it had code sequences such as:

   MVC HALFWORD,0(R3)
   LH    R2,HALFWORD

and
   STH R2,HALFWORD
   MVC 0(2,R3),HALFWORD

And this was *not* '60s code! It had been written around 1989!



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution

Quote:
>I think you can still get an S0C6 if you mis-align a CVB, CVD, CS, or CDS.
>Or if your target for an EX is not half-word aligned. Or if you branch to a
>odd address. But not for "normal" instructions. I remember going into an
>application where throughout it had code sequences such as:

[snip]

Alignment rules do not apply for CVB and CVD.  They do apply for CS and CDS, as well as for instruction fetch.

-- Steve Myers

The E-mail addresses in this message are private property.  Any use of them
to  send  unsolicited  E-mail  messages  of  a  commerical  nature  will be
considered trespassing,  and the originator of the message will be  sued in
small claims court in Camden County,  New Jersey,  for the  maximum penalty
allowed by law.



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution
From the Table of Contents of the most recent POP --

D.0           Appendix D.   Comparison between ESA/370 and ESA/390
D.1           New Facilities in ESA/390
  D.1.1         Access-List-Controlled Protection
  D.1.2         Branch and Set Authority
  D.1.3         Called-Space Identification
  D.1.4         Checksum
  D.1.5         Compare and Move Extended
  D.1.6         Concurrent Sense
  D.1.7         Immediate and Relative Instruction
  D.1.8         Move-Page Facility 2
  D.1.9         PER 2
  D.1.10        Perform Locked Operation
  D.1.11        Set Address Space Control Fast
  D.1.12        Square Root
  D.1.13        Storage-Protection Override
  D.1.14        String Instruction
  D.1.15        Subspace Group
  D.1.16        Suppression on Protection
D.2           Comparison of Facilities

Of course, some of these facilies were not in the initial ESA/390, like
Checksum, Compare and Move Extended, and maybe the string instructions.

-- Steve Myers

The E-mail addresses in this message are private property.  Any use of them
to  send  unsolicited  E-mail  messages  of  a  commerical  nature  will be
considered trespassing,  and the originator of the message will be  sued in
small claims court in Camden County,  New Jersey,  for the  maximum penalty
allowed by law.



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution

: Oh, BTW, I sometimes use a macro to generate a conditional branch to *+1
: to cause S0C6, when the "cannot happen" situation does happen. It's
: better than the ABEND macro (no registers or CC alteration), and slightly
: better than branching around "EX 0,*".

How do you fool the assembler diagnostic?  Do you use NOALIGN?  Perhaps
you generate this instruction with a DC?
--
| Edward E. Jaffe                | Voice:      (310) 338-0400 x318     |
| Mgr., Research & Development   | Facsimile:  (310) 338-0801          |

| 9841 Airport Blvd, Suite 700   | IBM Mail:   USS24J24 at IBMMAIL     |        
| Los Angeles, CA 90045          | Web page:   www.phoenixsoftware.com |



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution

: : Oh, BTW, I sometimes use a macro to generate a conditional branch to *+1
: : to cause S0C6, when the "cannot happen" situation does happen. It's
: : better than the ABEND macro (no registers or CC alteration), and slightly
: : better than branching around "EX 0,*".

: How do you fool the assembler diagnostic?  Do you use NOALIGN?  Perhaps
: you generate this instruction with a DC?

Probably he does.  I did.  DC X'47',X'cc',S(*-1) -- "The construction
of the macro is left as an exercise for the student..."
Mine is called "OOPS"...

For zapping modules to determine if code/logic is taking some
inappropriate path, I use X'1D1D' vs. the ol' time-worn X'0000'.
S0C1's can and do happen anywhere/everywhere.  But when the code
craters with an S0C6 -- bingo! -- I know right where it blew up.

Jonesy
MainFrame (IBM) since 1966
--
--
Marvin L. Jones  jonz<AT>rmi.net
Gunnison, Colorado
510 days to go until the Year 2000



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution
My guess would be DC X'47F0',S(*+1)

Bob

Quote:


> : Oh, BTW, I sometimes use a macro to generate a conditional branch to *+1
> : to cause S0C6, when the "cannot happen" situation does happen. It's
> : better than the ABEND macro (no registers or CC alteration), and slightly
> : better than branching around "EX 0,*".

> How do you fool the assembler diagnostic?  Do you use NOALIGN?  Perhaps
> you generate this instruction with a DC?
> --
> | Edward E. Jaffe                | Voice:      (310) 338-0400 x318     |
> | Mgr., Research & Development   | Facsimile:  (310) 338-0801          |

> | 9841 Airport Blvd, Suite 700   | IBM Mail:   USS24J24 at IBMMAIL     |
> | Los Angeles, CA 90045          | Web page:   www.phoenixsoftware.com |



Wed, 24 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution

Quote:

>>Not yet mentioned...  Data boundry alignment stopped being
>>required with S/370.  Only privileged instructions could get an
>>0C_    AHHHHGG!!!! Been so long since I got one, I forget what the
>>program interrupt code is for boundry alignment...  ;-)

>It was 0C6, "specification exception," and good riddance to it!

With some trepidation, I have disagree.  I think BOOF was a goof.
Without it, a corrupted register problem was easier to diagnose because
you'd tend to get a S0C6 much closer to the real point of failure, as
opposed to with BOOF, you get S0C4 after your data, code, god only knows
what, has been overwritten and the abend point bears little or no
relation to where the error actually occurred.

----
Jeff

Windows may be slow, but at least it's hard to use.



Thu, 25 Jan 2001 03:00:00 GMT  
 Instruction Set Evolution

Quote:

>The same customer, who had 360/67 experience, noticed that the emulator
>used a LRA instruction so the unannounced virtual addressing was out of
>the bag.  Of course the control panel that displayed both real and
>logical addresses was another hint.

OK.... How does one figure this out.  The emulation of ICM & STCM would be easy
to understand.  If you're looking at the emulator and you see the code
necessary for the emulation of an new op-code (in this case, LRA) , how can you
know your're looking at a page table if you don't know what one does?


Thu, 25 Jan 2001 03:00:00 GMT  
 
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