Which is faster? 
Author Message
 Which is faster?

Just out of curiosity; and perhaps someone has
actually tried to determine this..

[Of course, disclaimer flags everywhere... I
understand that determining instruction timings
on a modern mainframe is difficult, etc...]

So, on to the opinion poll!

  If you have:

      DATA   DS   F

which would be faster to see if `DATA'
is non-zero:

       ICM  Rx,B'1111',DATA
       BNZ  target

  vs.

       L      Rx,DATA
       LTR  Rx,Rx
       BNZ  target

    - Thanks for your thoughts -
        - Dave Rivers -

--

Get your mainframe (370) `C' compiler at http://www.*-*-*.com/



Tue, 11 Feb 2003 03:00:00 GMT  
 Which is faster?
Huh?


Quote:
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>ZXIgYXQgaHR0cDovL3d3dy5kaWdudXMuY29tDQoNCg0K



Tue, 11 Feb 2003 03:00:00 GMT  
 Which is faster?

enlightened us:

Quote:
>Huh?


>>SnVzdCBvdXQgb2YgY3VyaW9zaXR5OyBhbmQgcGVyaGFwcyBzb21lb25lIGhhcw0KYWN0dWFs
>>bHkgdHJpZWQgdG8gZGV0ZXJtaW5lIHRoaXMuLg0KDQpbT2YgY291cnNlLCBkaXNjbGFpbWVy
>>IGZsYWdzIGV2ZXJ5d2hlcmUuLi4gSQ0KdW5kZXJzdGFuZCB0aGF0IGRldGVybWluaW5nIGlu
>>c3RydWN0aW9uIHRpbWluZ3MNCm9uIGEgbW9kZXJuIG1haW5mcmFtZSBpcyBkaWZmaWN1bHQs
>>IGV0Yy4uLl0NCg0KU28sIG9uIHRvIHRoZSBvcGluaW9uIHBvbGwhDQoNCiAgSWYgeW91IGhh
>>dmU6DQoNCiAgICAgIERBVEEgICBEUyAgIEYNCg0Kd2hpY2ggd291bGQgYmUgZmFzdGVyIHRv
>>IHNlZSBpZiBgREFUQScNCmlzIG5vbi16ZXJvOg0KDQogICAgICAgSUNNICBSeCxCJzExMTEn
>>LERBVEENCiAgICAgICBCTlogIHRhcmdldA0KDQogIHZzLg0KDQogICAgICAgTCAgICAgIFJ4
>>LERBVEENCiAgICAgICBMVFIgIFJ4LFJ4DQogICAgICAgQk5aICB0YXJnZXQNCg0KDQogICAg
>>LSBUaGFua3MgZm9yIHlvdXIgdGhvdWdodHMgLQ0KICAgICAgICAtIERhdmUgUml2ZXJzIC0N
>>Cg0KDQotLQ0Kcml2ZXJzQGRpZ251cy5jb20gICAgICAgICAgICAgICAgICAgICAgICAgV29y
>>azogKDkxOSkgNjc2LTA4NDcNCkdldCB5b3VyIG1haW5mcmFtZSAoMzcwKSBgQycgY29tcGls
>>ZXIgYXQgaHR0cDovL3d3dy5kaWdudXMuY29tDQoNCg0K

Steve (great name!),

I don't know why you couldn't read David's message.  Must be a snafu
on your newserver, but here's what he posted:

Just out of curiosity; and perhaps someone has
actually tried to determine this..

[Of course, disclaimer flags everywhere... I
understand that determining instruction timings
on a modern mainframe is difficult, etc...]

So, on to the opinion poll!

  If you have:

      DATA   DS   F

which would be faster to see if `DATA'
is non-zero:

       ICM  Rx,B'1111',DATA
       BNZ  target

  vs.

       L      Rx,DATA
       LTR  Rx,Rx
       BNZ  target

    - Thanks for your thoughts -
        - Dave Rivers -

Regards,

          ////
         (o o)
-oOO--(_)--OOo-

Always take time to stop and smell the roses... and sooner
or later, you'll inhale a bee.

Boycott Mitsubishi Industries
For more info, please see:  
http://www.ran.org/ran/ran_campaigns/mitsubishi/background.html

Remove nospam to email me.

 Steve



Tue, 11 Feb 2003 03:00:00 GMT  
 Which is faster?
<snip>
Quote:
> So, on to the opinion poll!

>   If you have:

>       DATA   DS   F

> which would be faster to see if `DATA'
> is non-zero:

>        ICM  Rx,B'1111',DATA
>        BNZ  target

>   vs.

>        L      Rx,DATA
>        LTR  Rx,Rx
>        BNZ  target

>     - Thanks for your thoughts -
>         - Dave Rivers -

<snip>

It actually depends on which machine you are running on.  If the
machine is cached & pipelined, the apparent execution time would
be faster with the ICM.  Reason:  The machine has to fetch the
instruction from the cache (we are assuming all instructions in
the cache at this point).  Now it must do address computation,
then data fetch, store to register w/ test, set CC.  As soon as
the the instruction fetch is complete, the instruction moves to
the next stage in the pipe, so the next instruction is fetched.
Say that this is the BNZ.  Then it goes through address
computation, and data fetch (which in this case is already
accomplished for the BNZ).  Now we must effectively mark time
until the CC is available, which allows us to store into the IC
(instruction address of the PSW) so that the next Instruction
fetch can happen (and possibly flush any other instructions in
the pipe with their "partial completions").

The second one would be, instruction fetch, address computation,
data fetch, store into register.  Instruction fetch, hold for
register storage completion from prior instruction, test and CC
set.  Instruction fetch, address computation, wait for CC update,
store to IC and flush pipe and "partial completions".

Now, where does the CC update take place?  How many stages are in
the machine's pipe?  What optimizations are available?

Knowing specifically how the machine is constructed will allow
one to determine which set of instructions will execute faster.
However, the apparent results on a given pipelined machine could
go either way.  Knowing the number of stages on a few machines,
I'd say that the ICM & BNZ combination will be easier to read
(humanly & understand) and will complete quicker (causing fewer
pipe flushes).

--
Steve Thompson
OSP LLC
330/335-9907 office
330/334-2097 fax

Remove "_" in email address to contact me -- anti-spam measures
in use



Tue, 11 Feb 2003 03:00:00 GMT  
 Which is faster?


:>Just out of curiosity; and perhaps someone has
:>actually tried to determine this..

:>[Of course, disclaimer flags everywhere... I
:>understand that determining instruction timings
:>on a modern mainframe is difficult, etc...]

:>So, on to the opinion poll!

:>  If you have:

:>      DATA   DS   F

:>which would be faster to see if `DATA'
:>is non-zero:

:>       ICM  Rx,B'1111',DATA
:>       BNZ  target

:>  vs.

:>       L      Rx,DATA
:>       LTR  Rx,Rx
:>       BNZ  target

My understanding based on a discussion in IBM-MAIN was that with aligned data
the L/LTR sequence is slightly faster, but not significantly.

The ICM uses two bytes less of code.

Either one is pretty clear. Use whichever you prefer.

--


http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel



Thu, 13 Feb 2003 06:23:48 GMT  
 
 [ 5 post ] 

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